A question on computer systems design

What have you built or do you want to design to go with your replica 1

A question on computer systems design

Postby Juz10mac » Sep Mon 24, 2007 9:42 pm

Okay, I apologize. This isn't exactly Replica I, but I think this will still be the best place to get an answer to my question. The Replica I has sparked my interest in computer systems and their design.

I've been trying to learn a little more about computer systems, and I want to try my hand at designing my own system. I chose a Motorola 68000 processor. I have a question: I'm in the middle of researching how to select SRAM and EEPROM. The processor operates at 8MHz. The SRAM is 70ns and EEPROM is 200ns. When I do the math, the processor will be done with its cycle well before data is done being read from the EEPROM. The logic is chip enable, write enable, output enable... Here's my question: Do I need to select chips that are fast enough that they can be read in one processor cycle, or will the processor 'know' when the data is on the bus (so there is no chance that it will miss the data), or is there some way to get an output conformation from the chip that can be sent to the processor. So really what I'm asking is how do I make my processor talk to my memory if it will be a slow access.
I'm still learning, and still have quite a bit more research to do, but I'm very determined and appreciate any help.

Thanks,
Justin
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Postby Tsargon » Sep Fri 28, 2007 10:09 pm

Justin,

From what I understand, each CPU has some form of control line or combination of lines indicating that the bus operation is complete.

For example, the 6502 has the Ready - RDY line. The datasheets I have say "This feature allows microprocessor interfacing with low speed PROMS as well as fast (max. 2 cycle) Direct Memory Access (DMA)."

For the 68000, see the Data Transfer ACK - /DTACK line. The datasheet (PDF warning) I have on the 68000 says "This input signal indicates the completion of the data transfer. When the processor recognizes /DTACK during a read cycle, data is latched, and the bus cycle is terminated. When /DTACK is recognized during a write cycle, the bus cycle is terminated."

In your specific case, the 70ns SRAM should be fine for an 8MHz processor (125ns/clock cycle), but the 200ns EEPROM will need to tell the CPU that the data transfer is complete via the /DTACK line.

I hope this helps!
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Postby Juz10mac » Sep Sat 29, 2007 2:42 pm

Thanks! That does help. I think that may be just what I needed; I'll look into it.
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