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EEPROM Burner Question

PostPosted: Jan Tue 04, 2011 12:45 pm
by wmmullaney
I've been studying the 1 chip eeprom burner circuit Vince designed with my limited electronics knowledge, and I'm stuck.

Here is the circuit:

I understand the bottom half, that's all clear. With the top, it appears to enable the chip when the address range is anywhere except both the A and B blocks at the same time. The processor can't address two locations at once, so it serves no purpose? In addition to that, the ROM will be written to at any 8k block address. (0000.1fff, 2000.3fff ect..) Is this an error in the schematic, or am I missing something obvious? A NOR gate would do the trick there, enabling the chip in the A-B range. But that would make it two chips and waste several gates. You could build the circuit entirely with nor gates, but you would have to share phi2 for reading and writing. Is that ok? Is phi2 high when the cpu reads as well as writes?

I'd like to build such a programmer on my replica, so any help is greatly appreciated :wink:


Re: EEPROM Burner Question

PostPosted: Jan Tue 04, 2011 1:09 pm
by Kallikak
If you look at the Replica schematic you will see that A000 is low for addresses Axxx, and similarly B000 is low for Bxxx. The two NAND gates make an AND on these inputs implying CE is high *except* when A000 and B000 are not both high, i.e. except when addressing somewhere in the range A000-BFFF. This is as required for writing to the EEPROM.


Re: EEPROM Burner Question

PostPosted: Jan Tue 04, 2011 3:25 pm
by wmmullaney
Haha, oh, that makes sense. I didn't realize those were active low, shouldn't they have bars over them to denote that?

Thanks so much!

Re: EEPROM Burner Question

PostPosted: Dec Mon 26, 2011 12:58 am
by renejm
Here is a 4K EEPROM board that uses two 2816 to fill the space from 0xc000-0xcfff. It can be attached to any of the bank selects and works really well for me.

This was created for a computer architecture class I will be teaching with the Replica-1 in my lab.

Jim Reneau -